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#  xcm-009-LX15 sdram test 
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Net TP_A<0>  LOC="D26";  ## CN2.17
Net TP_A<1>  LOC="D25";  ## CN2.18
Net TP_A<2>  LOC="C26";  ## CN2.19
Net TP_A<3>  LOC="C25";  ## CN2.20
Net TP_A<4>  LOC="A24";  ## CN2.21
Net TP_A<5>  LOC="B24";  ## CN2.22
Net TP_A<6>  LOC="A23";  ## CN2.23
Net TP_A<7>  LOC="B23";  ## CN2.24
##
Net TP_A<8>  LOC="A22";  ## CN2.27
Net TP_A<9>  LOC="A21";  ## CN2.28
Net TP_A<10> LOC="B21";  ## CN2.29
Net TP_A<11> LOC="A20";  ## CN2.30
Net TP_A<12> LOC="B20";  ## CN2.31
##
Net TP_RAS LOC="AD1"; ## IOB41 CN1.58
Net TP_CAS LOC="AD2"; ## IOB42 CN1.59
Net TP_WE  LOC="AC1"; ## IOB43 CN1.60
Net TP_CS  LOC="AC2"; ## IOB44 CN1.61
Net TP_1   LOC="AD3"; ## IOB45 CN1.62
Net TP_2   LOC="AB1";  ## IOB46 CN1.63
Net TP_3   LOC="AA1";  ## IOB47 CN1.64
## System level constraints
Net ex_sys_clk_pin TNM_NET = ex_sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20833 ps HIGH 50 %;
Net ex_sys_clk_pin PERIOD = 20833 ps;

NET "ex_sys_clk_pin" LOC = "A12";


# GCLK3 48MHz
### Net ex_sys_clk_pin LOC=A12 ;
#GCLK1 18.432MHz
#### Module RS232 constraints
Net fpga_0_RS232_RX_pin LOC="H25" ;
Net fpga_0_RS232_TX_pin LOC="H26" ;

# SDRAM CLOCK Feedback and SDRAM-CLOCK
Net sdram_clk_fb_pin LOC="C15" ;	# GCLK2
NET fpga_0_Generic_SDRAM_SDRAM_Clk_pin  LOC = "G5"  ; 


#### Module Generic_SDRAM constraints
# SDRAM
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<12>  LOC = "F23"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<11>  LOC = "G21"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<10>  LOC = "E24"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<9>   LOC = "E22"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<8>   LOC = "D15"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<7>   LOC = "C16"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<6>   LOC = "D16"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<5>   LOC = "C17"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<4>   LOC = "E17"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<3>   LOC = "C19"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<2>   LOC = "G24"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<1>   LOC = "D18"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<0>   LOC = "C20"  ;
#
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<15>  LOC = "F16"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<14>  LOC = "F17"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<13>  LOC = "F18"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<12>  LOC = "G17"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<11>  LOC = "F19"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<10>  LOC = "G18"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<9>   LOC = "G19"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<8>   LOC = "F20"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<7>   LOC = "E20"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<6>   LOC = "E18"  ;
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<5>   LOC = "G3"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<4>   LOC = "H3"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<3>   LOC = "G2"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<2>   LOC = "H2"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<1>   LOC = "G1"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<0>   LOC = "H1"  ; 

#
NET fpga_0_Generic_SDRAM_SDRAM_DQM_pin<1>  LOC = "G20" ; ##DQML
NET fpga_0_Generic_SDRAM_SDRAM_DQM_pin<0>  LOC = "E21" ; ##DQMU
#
NET fpga_0_Generic_SDRAM_SDRAM_RASn_pin  LOC = "H23"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_CASn_pin  LOC = "H22"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_WEn_pin  LOC = "H21"  ;
NET fpga_0_Generic_SDRAM_SDRAM_CKE_pin  LOC = "D19"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_CSn_pin  LOC = "G22" ; 
#
NET fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin<1>  LOC = "H24"  ; 
NET fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin<0>  LOC = "G23"  ; 
####