--*** *-- --** HumanData Ltd. **-- --* by K.N ***-- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TX is Port ( CLK : in std_logic; RST : in std_logic; CE : in std_logic; WR : in std_logic; DI : in std_logic_vector(7 downto 0); RDY : out std_logic; TXD : out std_logic ); end TX; architecture RTL of TX is signal DI_REG : std_logic_vector( 7 downto 0 ); signal LD : std_logic; signal CBIT : integer range 0 to 9; begin process( CLK, RST ) begin if( RST = '1') then LD <= '0'; RDY <= '0'; CBIT <= 0 ; TXD <= '1'; elsif( CLK'event and CLK='1') then if( WR = '1' ) then RDY <= '1'; LD <= '1'; DI_REG <= DI; elsif( CE = '1' and LD = '1' ) then case CBIT is when 0 => TXD <= '0'; CBIT <= CBIT + 1; when 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => TXD <= DI_REG(0); DI_REG <= '1' & DI_REG(7 downto 1); CBIT <= CBIT + 1; when others => RDY <= '0'; TXD <= '1'; LD <= '0'; CBIT <= 0; end case; end if; end if; end process; end RTL;