/***                 */
/**  RS232C_CLKGEN  **/
/*                 ***/
module RS232C_CLKGEN( CK, RST, TX_EN, RX_EN );

input  CK, RST;
output TX_EN, RX_EN;
reg    [7:0] TX_CNT;
reg    [3:0] RX_CNT;

always @( posedge CK )
	if( RST )
		RX_CNT <= 4'h0;
	else if( RX_CNT == 4'h9 ) // 9
		RX_CNT <= 4'h0;
	else
		RX_CNT <= RX_CNT + 4'h1;

always @( posedge CK )
	if( RST )
		TX_CNT <= 8'h0;
	else if( TX_CNT == 8'h9F ) // 159
		TX_CNT <= 8'h0;
	else
		TX_CNT <= TX_CNT + 8'h1;

	assign RX_EN = ( RX_CNT == 4'h9 ) ;
	assign TX_EN = ( TX_CNT == 8'h9F ) ;

endmodule

/***             */
/**  RS232C_TX  **/
/*             ***/
module RS232C_TX( CK, RST, ENABLE, WR, DIN, DOUT ) ;

input  CK, RST, ENABLE, WR;
input  [7:0] DIN;
output DOUT;
reg    DOUT;
reg    LOAD;
reg    [7:0] SERIAL;
reg    [3:0] CBIT;


always @( posedge CK ) begin
	if( RST ) begin
		DOUT <= 1'b1;
		CBIT <= 4'h0;
	end
	else if( WR ) begin
		 LOAD   <= 1'b1;
		 SERIAL <= DIN;
	end
	else if( ENABLE && LOAD ) begin
		case( CBIT )
 	   	0 : 
			begin
				DOUT <= 1'b0;
				CBIT <= CBIT + 4'h1;
			end
			1,2,3,4,5,6,7,8 :
		 	begin
				DOUT   <= SERIAL[0];
				SERIAL <= { 1'b1, SERIAL[7:1]};
				CBIT   <= CBIT + 4'h1;
			end
			9 :
			begin
				DOUT  <= 1'b1;
				CBIT  <= 4'h0;
				LOAD  <= 1'b0;
			end
			default : begin
				DOUT <= 1'b1;
				CBIT <= 4'h0;
			end
		endcase
	end
end

endmodule

/***             */
/**  RS232C_RX  **/
/*             ***/
module RS232C_RX( CK, RST, CE, DIN, DOUT, RD ) ;

input  CK, RST, CE, DIN;
output [7:0] DOUT;
output RD;
reg    IRD;
reg    SERIAL, START;
reg    [7:0] PARALLEL;
reg    [7:0] DOUT;
reg    [7:0] CBIT;

always @( posedge CK ) begin
	if( RST ) begin
		DOUT     <= 8'h0;
		CBIT     <= 8'h0;
		PARALLEL <= 8'h0;
		IRD      <= 1'b0;
		START    <= 1'b0;
	end 
	else begin
		if( CE ) begin
			IRD <= 1'b0;

			if( !START ) begin
				if( !DIN ) 
			 		START    <= 1'b1;
			end
			else begin
				SERIAL <= DIN;

				case( CBIT )
					// START BIT
					6 :
					begin
						if( SERIAL == 1 ) 
				 			START <= 1'b0;
						else begin
							CBIT  <= CBIT + 8'h1;
						end
					end
					// DATA BIT
					22,38,54,70,86,102,118,134 :
					begin
						CBIT     <= CBIT + 8'h1;
						PARALLEL <= { SERIAL, PARALLEL[7:1] };
					end
					// STOP BIT
					142 :
					begin
						CBIT     <= 8'h0;
						DOUT     <= PARALLEL;
						START    <= 1'b0;
						IRD      <= 1'b1;
					end
					default :
						CBIT <= CBIT + 8'h1;
				endcase
			end
		end
	end
end

assign RD = IRD & CE;

endmodule