/*** */ /** MEMORY_CONTROL **/ /* ***/ module MEMORY_CONTROL( CLK, RST, RDSTB, IN_ASCII, OUT_ADRS, OUT_HIBYTE, OUT_LOBYTE ); input CLK, RST, RDSTB; input [7:0] IN_ASCII; output [7:0] OUT_ADRS; output [7:0] OUT_HIBYTE; output [7:0] OUT_LOBYTE; reg [ 3:0] HALF_ADRS ; reg [ 7:0] ADRS; reg [15:0] MEMORY_IN; reg MEMORY_WE; wire [15:0] MEMORY_OUT; reg [7:0] OUT_ADRS; reg [7:0] OUT_HIBYTE; reg [7:0] OUT_LOBYTE; reg [ 3:0] BIT4; reg [ 7:0] BIT8; reg [11:0] BIT12; reg [ 3:0] TERM_CNT; wire [ 3:0] HEX; parameter [7:0] ASC_W = 8'h57; parameter [7:0] ASC_R = 8'h52; parameter [7:0] ASC_CR = 8'h0D; RAM U0( CLK, MEMORY_WE, ADRS, MEMORY_IN, MEMORY_OUT ); CONV_ASCII_TO_BIN U1( IN_ASCII, HEX ); // STATE MACHINE // MEMORY READ / WRITE always @( posedge CLK ) begin if( RST ) TERM_CNT <= 1'b0; else if( RDSTB ) begin MEMORY_WE <= 1'b0; case( TERM_CNT ) 0 : begin if( IN_ASCII == ASC_R || IN_ASCII == ASC_W ) TERM_CNT <= 1'b1; else TERM_CNT <= 1'b0; end 1 : begin HALF_ADRS <= HEX; TERM_CNT <= TERM_CNT + 1'b1; end 2 : begin ADRS <= { HALF_ADRS , HEX }; TERM_CNT <= TERM_CNT + 1'b1; end 3 : begin if( IN_ASCII == ASC_CR ) begin // READ OUT_ADRS <= ADRS; // ADDRESS OUT_HIBYTE <= MEMORY_OUT[15:8]; // LOWORD OUT_LOBYTE <= MEMORY_OUT[ 7:0]; // HIWORD TERM_CNT <= 1'b0; end else begin BIT4 <= HEX; TERM_CNT <= TERM_CNT + 1; end end 4 : begin BIT8 <= { BIT4 , HEX }; TERM_CNT <= TERM_CNT + 3'b001; end 5 : begin BIT12 <= { BIT8 , HEX }; TERM_CNT <= TERM_CNT + 3'b001; end 6 : begin MEMORY_IN <= { BIT12 , HEX }; TERM_CNT <= TERM_CNT + 3'b001; end 7 : begin if( IN_ASCII == ASC_CR ) begin OUT_ADRS <= ADRS; // ADDRESS OUT_HIBYTE <= MEMORY_OUT[15:8]; // LOWORD OUT_LOBYTE <= MEMORY_OUT[ 7:0]; // HIWORD MEMORY_WE <= 1'b1; TERM_CNT <= 1'b0; end else begin OUT_ADRS <= 8'hxx; // ADDRESS OUT_HIBYTE <= 8'hxx; // LOWORD OUT_LOBYTE <= 8'hxx; // HIWORD MEMORY_WE <= 1'b0; TERM_CNT <= 3'b000; end end default : begin MEMORY_WE <= 1'b0; TERM_CNT <= 3'b000; OUT_ADRS <= 8'h00; // ADDRESS OUT_HIBYTE <= 8'h00; // LOWORD OUT_LOBYTE <= 8'h00; // HIWORD end endcase end end endmodule /*** */ /** RAM **/ /* ***/ module RAM( CLK, WE, ADRS, DI, DO ); input CLK, WE; input [ 7:0] ADRS; input [15:0] DI; output [15:0] DO; reg [15:0] MEM [255:0]; reg [ 7:0] READ_ADRS; always @( posedge CLK ) begin if( WE ) MEM[ADRS] <= DI; READ_ADRS <= ADRS; end assign DO = MEM[ READ_ADRS ]; endmodule /* ***/ /** CONV_ASCII_TO_BIN **/ /*** */ module CONV_ASCII_TO_BIN( ASCII, BYTE ); input [7:0] ASCII; output [3:0] BYTE; reg [3:0] BYTE; parameter [7:0] ASC_ZERO = 8'h30; parameter [7:0] ASC_NINE = 8'h39; parameter [7:0] ASC_UA = 8'h41; parameter [7:0] ASC_UF = 8'h46; parameter [7:0] ASC_LA = 8'h61; parameter [7:0] ASC_LF = 8'h66; always @( ASCII ) begin if( ASC_ZERO <= ASCII && ASCII <= ASC_NINE ) BYTE <= ASCII[3:0]; else if( ASC_UA <= ASCII && ASCII <= ASC_UF ) BYTE <= ASCII[3:0] + 4'b1001; else if( ASC_LA <= ASCII && ASCII <= ASC_LF ) BYTE <= ASCII[3:0] + 4'b1001; else BYTE <= 4'bxxxx; end endmodule