/***           */
/**  SEG_MUX  **/
/*           ***/
module SEG_CTL( CLK, CE, RST, DATA_A, DATA_B, DATA_C, DATA_D, DATA_E, DATA_F, DATA_OUT, SA );
	input        CLK, CE, RST;
	input  [3:0] DATA_A, DATA_B, DATA_C;
	input  [3:0] DATA_D, DATA_E, DATA_F;
	output [6:0] DATA_OUT;
	output [5:0] SA;

	wire   [6:0] DEC_A, DEC_B, DEC_C;
	wire   [6:0] DEC_D, DEC_E, DEC_F;

	wire   [2:0] SEL;

	DECODER U0( DATA_A, DEC_A );
	DECODER U1( DATA_B, DEC_B );

	DECODER U2( DATA_C, DEC_C );
	DECODER U3( DATA_D, DEC_D );

	DECODER U4( DATA_E, DEC_E );
	DECODER U5( DATA_F, DEC_F );
	
	SEG_MUX U6( DEC_A, DEC_B, DEC_C, DEC_D, DEC_E, DEC_F, DATA_OUT, SEL, SA);
	SEG_CNT U7( CLK, CE, RST, SEL );

endmodule


/***           */
/**  SEG_MUX  **/
/*           ***/
module SEG_MUX( DATA_A, DATA_B, DATA_C, DATA_D, DATA_E, DATA_F, DATA_OUT, SEL, SA);
input  [6:0] DATA_A, DATA_B, DATA_C;
input  [6:0] DATA_D, DATA_E, DATA_F;
input  [2:0] SEL;
output [6:0] DATA_OUT;
output [5:0] SA;

function [5:0] DEC_SA;
	input [2:0] SEL;

	case ( SEL )
		3'h0: DEC_SA = 6'b0zzzzz; 
		3'h1: DEC_SA = 6'bz0zzzz;
		3'h2: DEC_SA = 6'bzz0zzz; 
		3'h3: DEC_SA = 6'bzzz0zz; 
		3'h4: DEC_SA = 6'bzzzz0z;
		3'h5: DEC_SA = 6'bzzzzz0; 
		default : DEC_SA   = 6'bzzzzzz;
	endcase
endfunction

function [6:0] DEC_DATA;	 
	input [6:0] DATA_A, DATA_B, DATA_C;
	input [6:0] DATA_D, DATA_E, DATA_F;
	input [2:0] SEL;

	case ( SEL )
		3'h0: DEC_DATA = DATA_A; 
		3'h1: DEC_DATA = DATA_B;
		3'h2: DEC_DATA = DATA_C;
		
		3'h3: DEC_DATA = DATA_D;
		3'h4: DEC_DATA = DATA_E;
		3'h5: DEC_DATA = DATA_F; 
		
		default : DEC_DATA = 7'bxxxxxxx;
	endcase
endfunction

assign DATA_OUT = DEC_DATA( DATA_A, DATA_B, DATA_C, DATA_D, DATA_E, DATA_F, SEL );	
assign SA       = DEC_SA( SEL );

endmodule

/***           */
/**  DECODER  **/
/*           ***/
module DECODER( D_IN, D_OUT );
    input    [3:0] D_IN;
    output   [6:0] D_OUT;

	 function [6:0] DEC;
	 input [3:0] D_IN;
	 case ( D_IN )
	 	4'h0: DEC = 7'b1000000; // 0
		4'h1: DEC = 7'b1111001; // 1
		4'h2: DEC = 7'b0100100; // 2
		4'h3: DEC = 7'b0110000; // 3
		4'h4: DEC = 7'b0011001; // 4
		4'h5: DEC = 7'b0010010; // 5
		4'h6: DEC = 7'b0000010; // 6
		4'h7: DEC = 7'b1111000; // 7
		4'h8: DEC = 7'b0000000; // 8
		4'h9: DEC = 7'b0010000; // 9
		4'ha: DEC = 7'b0001000; // a
		4'hb: DEC = 7'b0000011; // b
		4'hc: DEC = 7'b1000110; // c
		4'hd: DEC = 7'b0100001; // d
		4'he: DEC = 7'b0000110; // e
		4'hf: DEC = 7'b0001110; // f
		default : DEC = 7'bxxxxxxx;
   endcase
	endfunction

	assign D_OUT = DEC( D_IN );

endmodule

/***           */
/**  SEG_CNT  **/
/*           ***/
module SEG_CNT( CLK, CE, RST, SEL );
	input         CLK, CE, RST;
	output  [2:0] SEL;
	reg     [2:0] SEL;

	always @( posedge CLK ) begin
		if( RST )
			SEL <= 0;
		else if( CE )
			if( SEL == 3'h5 )
				SEL <= 3'h0;
			else
				SEL <= SEL + 1'b1;
	end

endmodule