/***                */
/**  USB ECHO TOP  **/
/*                ***/
module USB_vrg( CLK, PSW3, RXF_N, TXE_N, RD_N, WR, USB_DATA );

input       CLK, PSW3;
input       RXF_N, TXE_N;
output      RD_N, WR;
inout [7:0] USB_DATA;

wire        BUSY, READY, ENB;
wire        RST;
wire  [7:0] DATA; 

assign READY = ~BUSY;
assign RST = ~PSW3;

USB_ARBITER U0 
		  ( .CLK(CLK),
			 .RST(RST),

			 .RXF_N(RXF_N), // IN
			 .TXE_N(TXE_N), // IN
			 .RD_N(RD_N),   // OUT
			 .WR(WR),       // OUT

			 .BUS_BUSY(BUSY),   // OUT
			 .TG_READY(READY),  // IN

			 .USB_DATA(USB_DATA), 

			 .TG_DO(DATA),
			 .TG_DI(DATA), 
			 .TG_RD(ENB),
			 .TG_WR(ENB) );

endmodule