2002/07/25(更新日 2021年05月12日)

  _____   _____ ___ ___ ___ ___ 
 / __\ \ / / _ \ _ \ __/ __/ __|
| (__ \ ^ /|  _/   / _|\__ \__ \
 \___| |_| |_| |_|_\___|___/___/ TIMING TECHNOLOGY
==================================================
Modification Date: Jul/25/2002
Comments: 
Customer: XSP009
FAE: 
P/N: CY2071ASL-XXX
                     ______________    
                   _|     \__/     |_                   
             CLKA |_| 1          8 |_| FS               
                   _|              |_                   
              GND |_| 2          7 |_| VDD              
                   _|   CY2071A    |_                   
           XTALIN |_| 3          6 |_| CLKC             
                   _|              |_                   
          XTALOUT |_| 4          5 |_| CLKB             
                    |______________|   

Reference Input: 16.00000 MHz
Operating Voltage: 3.3V
PLL(0): Desired = 66 MHz
PLL(1): Desired = 80 MHz
Smooth Slew: Off

OUTPUT CLK
=============================================================
|         |         |   Desired    |    Actual    |   PPM   |
=============================================================
| CLKA(0) |  (PLL)  |     66.00000 |     66.00000 |       0 |
|         |         |              |              |         |
| CLKB(0) | (PLL/2) |     33.00000 |     33.00000 |       0 |
|         |         |              |              |         |
| CLKC(0) | (PLL/4) |     16.50000 |     16.50000 |       0 |
|         |         |              |              |         |
| CLKA(1) |  (PLL)  |     80.00000 |     80.00000 |       0 |
|         |         |              |              |         |
| CLKB(1) | (PLL/2) |     40.00000 |     40.00000 |       0 |
|         |         |              |              |         |
| CLKC(1) | (PLL/4) |     20.00000 |     20.00000 |       0 |
=============================================================

Entry File: XSP009.ent
CHECKSUM: 227
(Generated by CyClocks(tm) 3.65 - Build #: 3.65.006)

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