--
--USB026_ARBITER FOR USB-026 VER 1
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity USB026_ARBITER is
	Port ( CLK : in  std_logic;
			 RST_N : in  std_logic;

			 RXF_N : in std_logic;
			 TXE_N : in std_logic;
			 RD_N  : out std_logic;
			 WR_N   : out std_logic;

			 LED0	   : out std_logic;
			 LED1    : out std_logic;
--			 TP_DIR : out std_logic;

			 FTUSBD     : in  std_logic_vector( 7 downto 0 );			
			 LUSBD    : out  std_logic_vector( 7 downto 0 );

--			 O_TG_LT    : out std_logic;
			 
			 VE    :out  std_logic;			 
			 READY : in  std_logic;			 
			 OSTB_N     : out std_logic; 
			 INSTB_N    : in  std_logic;
			 INACK_N : out std_logic
			
			 );
end USB026_ARBITER;

architecture RTL of USB026_ARBITER is

signal RXF_REG      : std_logic;
signal TXE_REG      : std_logic;
signal USBD : std_logic_vector( 7 downto 0 );
signal WRN_REG   : std_logic;
signal DIR : std_logic;
signal R_INACK_N : std_logic;
signal  INSTB_TG_WR : std_logic;

signal RST : std_logic;
  
type STATE_TYPE is ( PL_TG1, PL_TG2, 
                   TG1_R0, TG1_R1, TG1_R2,  
                   TG2_W0, TG2_W1, TG2_W2, TG2_W3	 );

signal STATE : STATE_TYPE;

begin

RST <= not RST_N;

LUSBD <= USBD;		
INACK_N <= R_INACK_N;


process( CLK, RST ) begin
	if ( RST ='1') then
		RXF_REG <= '0';
		TXE_REG <= '0';
		INSTB_TG_WR  <= '0';	
	elsif( CLK'event and CLK='1') then
		RXF_REG <= not RXF_N;
		TXE_REG <= not TXE_N;
		INSTB_TG_WR <= not INSTB_N;	
		VE <= DIR;
		WR_N <= WRN_REG;
	else
		NULL;
	end if;
end process;


process( CLK, RST ) begin
	if ( RST ='1') then
		LED1 <= '0';	
	elsif( CLK'event and CLK='1') then
		if( READY = '0' ) then 
				LED1 <= '0';	
	   else
				LED1 <= 'Z';	
		end if;
	else
		NULL;
	end if;
end process;



process( CLK, RST ) begin 
	if ( RST ='1') then
		USBD    <= "00000000";
		RD_N     <= '1';
		WRN_REG <= '1';
		STATE <= PL_TG1;
		DIR <= '0';	
		LED0 <= '0';
		R_INACK_N <= '1';
		OSTB_N  <= '1';			
	elsif( CLK'event and CLK='1') then

		case STATE is
			-- **
         -- ** Polling from TG1
			-- **
			when PL_TG1 => -- FROM-PC(OUTPUT)
				OSTB_N  <= '1';
				R_INACK_N <= '1';	
				if( RXF_REG='1' and READY ='1' ) then
					RD_N <= '0';
					STATE    <= TG1_R0;-- FROM-PC(OUTPUT)
				else						
					STATE <= PL_TG2;
				end if;					
			when PL_TG2 => -- TO-PC(INPUT)
				LED0 <= 'Z';
				OSTB_N  <= '1';
				if( INSTB_TG_WR='1') then
					STATE  <= TG2_W0;-- TO-PC(INPUT)
				else
					STATE <= PL_TG1;
				end if;
			--
			-- FROM-PC
			--
			---------------------------------------
			-- (OUTPUT)READ STATE MACHINE
			--------------------------------------
			when TG1_R0 =>
				DIR <= '0';
				RD_N     <= '0';
				USBD    <= FTUSBD;
				STATE <= TG1_R1;
			when TG1_R1 =>
				OSTB_N  <= '0';	
				DIR <= '0';
				RD_N     <= '1';
				STATE <= TG1_R2;
			when TG1_R2 =>
				OSTB_N  <= '0';	
				DIR <= '0';
				STATE <= PL_TG2;			
			--
			-- TO-PC
			--
			-------------------------------------
			--   (INPUT) WRITE STATE MACHINE  
			-------------------------------------
			when TG2_W0 =>
				LED0 <= '0'; 
				WRN_REG <= '1';
				DIR <='1';
				STATE <= TG2_W1;
			when TG2_W1 =>
				WRN_REG  <= '0'; 
				DIR <= '1';
				STATE <= TG2_W2;
			when TG2_W2 =>
				R_INACK_N <= '0';	
				WRN_REG  <= '0';
				DIR <= '1';
				if( TXE_REG = '0' ) then
					STATE<= TG2_W2;	
				else
					STATE<= TG2_W3;
				end if;		
			when TG2_W3 =>
				R_INACK_N <= '0';	
				WRN_REG  <= '1';
				DIR <= '0';
				if( INSTB_TG_WR='1' ) then
					STATE <= TG2_W3;
				else
					STATE <= PL_TG1;
				end if;								
			when others => STATE <= PL_TG1;
		end case;
	end if;
end process;




end RTL;