NEDXspl01 Project Status (08/07/2008 - 17:42:09)
Project File: NEDXspl01.ise Current State: Programming File Generated
Module Name: EDXSPL1_TOP
  • Errors:
No Errors
Target Device: xc2s100-5tq144
  • Warnings:
6 Warnings (0 filtered)
Product Version: ISE 10.1.02 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
NEDXspl01 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 48 2,400 2%  
Number of 4 input LUTs 70 2,400 2%  
Logic Distribution     
    Number of occupied Slices 59 1,200 4%  
    Number of Slices containing only related logic 59 59 100%  
    Number of Slices containing unrelated logic 0 59 0%  
Total Number of 4 input LUTs 106 2,400 4%  
        Number used as logic 70      
        Number used as a route-thru 36      
Number of bonded IOBs
Number of bonded 10 92 10%  
Number of GCLKs 1 4 25%  
Number of GCLKIOBs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent木 8 7 17:40:49 200804 Warnings (0 filtered)0
Translation ReportCurrent木 8 7 17:40:54 2008000
Map ReportCurrent木 8 7 17:40:58 200802 Warnings (0 filtered)2 Infos (0 filtered)
Place and Route ReportCurrent木 8 7 17:41:05 2008002 Infos (0 filtered)
Static Timing ReportCurrent木 8 7 17:41:07 2008003 Infos (0 filtered)
Bitgen ReportCurrent木 8 7 17:42:07 2008000

Date Generated: 08/07/2008 - 17:42:09
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