NEDXspl04 Project Status (08/07/2008 - 17:07:59)
Project File: NEDXspl04.ise Current State: Programming File Generated
Module Name: EDXSPL4_TOP
  • Errors:
 
Target Device: xc2s100-5tq144
  • Warnings:
 
Product Version: ISE 10.1.02 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
NEDXspl04 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 44 2,400 1%  
Number of 4 input LUTs 78 2,400 3%  
Logic Distribution     
    Number of occupied Slices 54 1,200 4%  
    Number of Slices containing only related logic 54 54 100%  
    Number of Slices containing unrelated logic 0 54 0%  
Total Number of 4 input LUTs 79 2,400 3%  
        Number used as logic 78      
        Number used as a route-thru 1      
Number of bonded IOBs
Number of bonded 26 92 28%  
Number of GCLKs 1 4 25%  
Number of GCLKIOBs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent木 8 7 17:07:33 2008   
Translation ReportCurrent木 8 7 17:07:40 2008   
Map ReportCurrent木 8 7 17:07:44 2008   
Place and Route ReportCurrent木 8 7 17:07:51 2008   
Static Timing ReportCurrent木 8 7 17:07:54 2008   
Bitgen ReportCurrent木 8 7 17:07:58 2008   

Date Generated: 08/07/2008 - 17:07:59
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