NEDXspl03 Project Status (08/07/2008 - 17:29:14) | |||
Project File: | NEDXspl03.ise | Current State: | Programming File Generated |
Module Name: | EDXSPL3_TOP |
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No Errors |
Target Device: | xc2s100-5tq144 |
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No Warnings |
Product Version: | ISE 10.1.02 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
NEDXspl03 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 26 | 2,400 | 1% | ||
Number of 4 input LUTs | 11 | 2,400 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 17 | 1,200 | 1% | ||
Number of Slices containing only related logic | 17 | 17 | 100% | ||
Number of Slices containing unrelated logic | 0 | 17 | 0% | ||
Total Number of 4 input LUTs | 11 | 2,400 | 1% | ||
Number of bonded IOBs | |||||
Number of bonded | 13 | 92 | 14% | ||
Number of GCLKs | 1 | 4 | 25% | ||
Number of GCLKIOBs | 1 | 4 | 25% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 木 8 7 17:27:29 2008 | 0 | 0 | 2 Infos (0 filtered) | |
Translation Report | Current | 木 8 7 17:27:35 2008 | 0 | 0 | 0 | |
Map Report | Current | 木 8 7 17:27:38 2008 | 0 | 0 | 2 Infos (0 filtered) | |
Place and Route Report | Current | 木 8 7 17:29:07 2008 | 0 | 0 | 2 Infos (0 filtered) | |
Static Timing Report | Current | 木 8 7 17:29:09 2008 | 0 | 0 | 3 Infos (0 filtered) | |
Bitgen Report | Current | 木 8 7 17:29:13 2008 | 0 | 0 | 0 |