NEDXspl02 Project Status (08/07/2008 - 17:54:59)
Project File: NEDXspl02.ise Current State: Programming File Generated
Module Name: EDXSPL2_TOP
  • Errors:
No Errors
Target Device: xc2s100-5tq144
  • Warnings:
7 Warnings (0 filtered)
Product Version: ISE 10.1.02 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
NEDXspl02 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 72 2,400 3%  
Number of 4 input LUTs 98 2,400 4%  
Logic Distribution     
    Number of occupied Slices 86 1,200 7%  
    Number of Slices containing only related logic 86 86 100%  
    Number of Slices containing unrelated logic 0 86 0%  
Total Number of 4 input LUTs 151 2,400 6%  
        Number used as logic 98      
        Number used as a route-thru 53      
Number of bonded IOBs
Number of bonded 12 92 13%  
Number of GCLKs 1 4 25%  
Number of GCLKIOBs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent木 8 7 17:54:35 200805 Warnings (0 filtered)1 Info (0 filtered)
Translation ReportCurrent木 8 7 17:54:40 2008000
Map ReportCurrent木 8 7 17:54:44 200802 Warnings (0 filtered)2 Infos (0 filtered)
Place and Route ReportCurrent木 8 7 17:54:51 2008002 Infos (0 filtered)
Static Timing ReportCurrent木 8 7 17:54:54 2008003 Infos (0 filtered)
Bitgen ReportCurrent木 8 7 17:54:58 2008000

Date Generated: 08/07/2008 - 17:54:59
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