NEDXspl04 Project Status (08/07/2008 - 17:07:59) | |||
Project File: | NEDXspl04.ise | Current State: | Programming File Generated |
Module Name: | EDXSPL4_TOP |
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Target Device: | xc2s100-5tq144 |
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Product Version: | ISE 10.1.02 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
NEDXspl04 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 44 | 2,400 | 1% | ||
Number of 4 input LUTs | 78 | 2,400 | 3% | ||
Logic Distribution | |||||
Number of occupied Slices | 54 | 1,200 | 4% | ||
Number of Slices containing only related logic | 54 | 54 | 100% | ||
Number of Slices containing unrelated logic | 0 | 54 | 0% | ||
Total Number of 4 input LUTs | 79 | 2,400 | 3% | ||
Number used as logic | 78 | ||||
Number used as a route-thru | 1 | ||||
Number of bonded IOBs | |||||
Number of bonded | 26 | 92 | 28% | ||
Number of GCLKs | 1 | 4 | 25% | ||
Number of GCLKIOBs | 1 | 4 | 25% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 木 8 7 17:07:33 2008 | ||||
Translation Report | Current | 木 8 7 17:07:40 2008 | ||||
Map Report | Current | 木 8 7 17:07:44 2008 | ||||
Place and Route Report | Current | 木 8 7 17:07:51 2008 | ||||
Static Timing Report | Current | 木 8 7 17:07:54 2008 | ||||
Bitgen Report | Current | 木 8 7 17:07:58 2008 |