NEDXspl03 Project Status (08/07/2008 - 17:29:14)
Project File: NEDXspl03.ise Current State: Programming File Generated
Module Name: EDXSPL3_TOP
  • Errors:
No Errors
Target Device: xc2s100-5tq144
  • Warnings:
No Warnings
Product Version: ISE 10.1.02 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
NEDXspl03 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 26 2,400 1%  
Number of 4 input LUTs 11 2,400 1%  
Logic Distribution     
    Number of occupied Slices 17 1,200 1%  
    Number of Slices containing only related logic 17 17 100%  
    Number of Slices containing unrelated logic 0 17 0%  
Total Number of 4 input LUTs 11 2,400 1%  
Number of bonded IOBs
Number of bonded 13 92 14%  
Number of GCLKs 1 4 25%  
Number of GCLKIOBs 1 4 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent木 8 7 17:27:29 2008002 Infos (0 filtered)
Translation ReportCurrent木 8 7 17:27:35 2008000
Map ReportCurrent木 8 7 17:27:38 2008002 Infos (0 filtered)
Place and Route ReportCurrent木 8 7 17:29:07 2008002 Infos (0 filtered)
Static Timing ReportCurrent木 8 7 17:29:09 2008003 Infos (0 filtered)
Bitgen ReportCurrent木 8 7 17:29:13 2008000

Date Generated: 08/07/2008 - 17:29:14
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