// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module DET1(
	CLK,
	INA,
	INB,
	DET
);

input	CLK;
input	INA;
input	INB;
output	DET;
reg	DET;

wire	BBINA;
wire	BBINB;
wire	BINA;
wire	BINB;
wire	BNA;
wire	BNB;
wire	NA;
wire	NB;
wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_9;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_8;




assign	SYNTHESIZED_WIRE_1 = NA ^ NB;

always@(posedge CLK)
begin
	begin
	DET <= SYNTHESIZED_WIRE_0;
	end
end
assign	NA = BINA & INB;
assign	NB = INA & BINB;

BIBUN	b2v_inst12(.INP(SYNTHESIZED_WIRE_1),
.CLK(CLK),.OUTP(SYNTHESIZED_WIRE_8));
assign	BNA = BBINA & SYNTHESIZED_WIRE_9;
assign	BNB = SYNTHESIZED_WIRE_10 & BBINB;

BIBUN	b2v_inst15(.INP(SYNTHESIZED_WIRE_10),
.CLK(CLK),.OUTP(BBINA));

BIBUN	b2v_inst16(.INP(SYNTHESIZED_WIRE_9),
.CLK(CLK),.OUTP(BBINB));

BIBUN	b2v_inst17(.INP(SYNTHESIZED_WIRE_6),
.CLK(CLK),.OUTP(SYNTHESIZED_WIRE_7));
assign	SYNTHESIZED_WIRE_6 = BNA ^ BNB;
assign	SYNTHESIZED_WIRE_10 =  ~INA;
assign	SYNTHESIZED_WIRE_9 =  ~INB;
assign	SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8;

BIBUN	b2v_inst8(.INP(INA),
.CLK(CLK),.OUTP(BINA));

BIBUN	b2v_inst9(.INP(INB),
.CLK(CLK),.OUTP(BINB));


endmodule