-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY BIBUN IS 
	port
	(
		INP :  IN  STD_LOGIC;
		CLK :  IN  STD_LOGIC;
		OUTP :  OUT  STD_LOGIC
	);
END BIBUN;

ARCHITECTURE bdf_type OF BIBUN IS 

signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	DFF_inst4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;


BEGIN 



process(CLK)
begin
if (rising_edge(CLK)) then
	SYNTHESIZED_WIRE_2 <= INP;
end if;
end process;

process(CLK)
begin
if (rising_edge(CLK)) then
	DFF_inst4 <= SYNTHESIZED_WIRE_2;
end if;
end process;

SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_0 AND DFF_inst4;

process(CLK)
begin
if (rising_edge(CLK)) then
	OUTP <= SYNTHESIZED_WIRE_1;
end if;
end process;

SYNTHESIZED_WIRE_0 <= NOT(SYNTHESIZED_WIRE_2);


END;