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#  xcm-005-1000 sdram test 
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## test point
Net TP_A0 LOC=E10;  ## IOB40 CN1.57
Net TP_RAS LOC=F10; ## IOB41 CN1.58
Net TP_CAS LOC=B10;  ## IOB42 CN1.59
Net TP_WE LOC=C10;   ## IOB43 CN1.60
Net TP_CS LOC=E11;  ## IOB44 CN1.61
Net TP_1 LOC=F11; ## IOB45 CN1.62
Net TP_2 LOC=D4;  ## IOB46 CN1.63
Net TP_3 LOC=E4;   ## IOB47 CN1.64


## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
Net sys_clk_pin PERIOD = 20833 ps;

# GCLK3 48MHz
Net sys_clk_pin LOC=AA11 ;

#### Module RS232 constraints

Net fpga_0_RS232_RX_pin LOC=M17 ;
Net fpga_0_RS232_TX_pin LOC=M18 ;

# SDRAM CLOCK Feedback and SDRAM-CLOCK
Net sdram_clk_fb_pin LOC=Y11 ;	# GCLK2
NET fpga_0_Generic_SDRAM_SDRAM_Clk_pin  LOC = W11 ; 


#### Module Generic_SDRAM constraints
# SDRAM
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<12>  LOC = "V8"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<11>  LOC = "W8"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<10>  LOC = "AA8"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<9>  LOC = "AB8"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<8>  LOC = "U9"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<7>  LOC = "V9"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<6>  LOC = "AA9"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<5>  LOC = "AB9"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<4>  LOC = "U10"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<3>  LOC = "V10"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<2>  LOC = "Y10"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<1>  LOC = "AA10"; 
NET fpga_0_Generic_SDRAM_SDRAM_Addr_pin<0>  LOC = "AB10";

#
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<15>  LOC = "U12"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<14>  LOC = "AA3"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<13>  LOC = "Y4"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<12>  LOC = "AA4"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<11>  LOC = "AB4"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<10>  LOC = "W5"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<9>  LOC = "Y5"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<8>  LOC = "V6"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<7>  LOC = "W6"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<6>  LOC = "Y6";
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<5>  LOC = "AA6"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<4>  LOC = "U7"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<3>  LOC = "V7"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<2>  LOC = "Y7"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<1>  LOC = "AA7"; 
NET fpga_0_Generic_SDRAM_SDRAM_DQ_pin<0>  LOC = "AB7"; 
#
NET fpga_0_Generic_SDRAM_SDRAM_DQM_pin<1>  LOC = "AB18" ; ##DQML
NET fpga_0_Generic_SDRAM_SDRAM_DQM_pin<0>  LOC = "AA18" ; ##DQMU
#
NET fpga_0_Generic_SDRAM_SDRAM_RASn_pin  LOC = "W17" ; 
NET fpga_0_Generic_SDRAM_SDRAM_CASn_pin  LOC = "AA17" ; 
NET fpga_0_Generic_SDRAM_SDRAM_WEn_pin  LOC = "Y18" ;
NET fpga_0_Generic_SDRAM_SDRAM_CKE_pin  LOC = "Y17"; 
NET fpga_0_Generic_SDRAM_SDRAM_CSn_pin  LOC = "V18"; 
#
NET fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin<1>  LOC = "U11" ; 
NET fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin<0>  LOC = "V11" ; 
####