------------------------------------------------------------------------------- -- xcm-005-1000 memory test top ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is port ( fpga_0_RS232_req_to_send_pin : out std_logic; fpga_0_RS232_RX_pin : in std_logic; fpga_0_RS232_TX_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_DQ_pin : inout std_logic_vector(0 to 15); fpga_0_Generic_SDRAM_SDRAM_Addr_pin : out std_logic_vector(0 to 12); fpga_0_Generic_SDRAM_SDRAM_DQM_pin : out std_logic_vector(0 to 1); fpga_0_Generic_SDRAM_SDRAM_WEn_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_CKE_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_CSn_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_CASn_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_RASn_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_Clk_pin : out std_logic; fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin : out std_logic_vector(0 to 1); sys_clk_pin : in std_logic; pin_sys_rst_pin : in std_logic; sdram_clk_fb_pin : in std_logic; dcm_sdram_LOCKED_pin : out std_logic; TP_A0 : out std_logic; -- IOB40 CN1.57 TP_RAS : out std_logic; -- IOB41 CN1.58 TP_CAS : out std_logic; -- IOB42 CN1.59 TP_WE : out std_logic; -- IOB43 CN1.60 TP_CS : out std_logic; -- IOB44 CN1.61 TP_1 : out std_logic; -- IOB45 CN1.62 TP_2 : out std_logic; -- IOB46 CN1.63 TP_3 : out std_logic -- IOB47 CN1.64 --- ); end top; architecture RTL of top is component arst is port ( CLK: in STD_LOGIC; RSTO: out STD_LOGIC ); end component; COMPONENT system_stub PORT( fpga_0_RS232_RX_pin : IN std_logic; sys_rst_pin : IN std_logic; sdram_clk_fb_pin : IN std_logic; sys_clk_pin : IN std_logic; fpga_0_Generic_SDRAM_SDRAM_DQ_pin : INOUT std_logic_vector(0 to 15); fpga_0_RS232_req_to_send_pin : OUT std_logic; fpga_0_RS232_TX_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_Addr_pin : OUT std_logic_vector(0 to 12); fpga_0_Generic_SDRAM_SDRAM_DQM_pin : OUT std_logic_vector(0 to 1); fpga_0_Generic_SDRAM_SDRAM_WEn_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_CKE_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_CSn_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_CASn_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_RASn_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_Clk_pin : OUT std_logic; fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin : OUT std_logic_vector(0 to 1); dcm_sdram_LOCKED_pin : OUT std_logic; Generic_SDRAM_SDRAM_Init_done_pin : OUT std_logic ); END COMPONENT; signal auto_rst: std_logic; -- signal SIG_0_Generic_SDRAM_SDRAM_DQ_pin : std_logic_vector(0 to 15); signal SIG_0_Generic_SDRAM_SDRAM_Addr_pin : std_logic_vector(0 to 12); signal SIG_0_Generic_SDRAM_SDRAM_DQM_pin : std_logic_vector(0 to 1); signal SIG_0_Generic_SDRAM_SDRAM_WEn_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_CKE_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_CSn_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_CASn_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_RASn_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_Clk_pin : std_logic; signal SIG_0_Generic_SDRAM_SDRAM_BankAddr_pin : std_logic_vector(0 to 1); signal monit_data : std_logic_vector(0 to 15); signal internal_obf_clk: std_logic; signal dummy_node: std_logic; ---------------------------------- begin u1 : ARST port map( CLK => sys_clk_pin, RSTO => auto_rst ); cpu1: system_stub PORT MAP( sdram_clk_fb_pin => sdram_clk_fb_pin, fpga_0_RS232_req_to_send_pin => fpga_0_RS232_req_to_send_pin, fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin, fpga_0_RS232_TX_pin => fpga_0_RS232_TX_pin, fpga_0_Generic_SDRAM_SDRAM_DQ_pin => SIG_0_Generic_SDRAM_SDRAM_DQ_pin, fpga_0_Generic_SDRAM_SDRAM_Addr_pin => SIG_0_Generic_SDRAM_SDRAM_Addr_pin, fpga_0_Generic_SDRAM_SDRAM_DQM_pin => SIG_0_Generic_SDRAM_SDRAM_DQM_pin, fpga_0_Generic_SDRAM_SDRAM_WEn_pin => SIG_0_Generic_SDRAM_SDRAM_WEn_pin, fpga_0_Generic_SDRAM_SDRAM_CKE_pin => SIG_0_Generic_SDRAM_SDRAM_CKE_pin, fpga_0_Generic_SDRAM_SDRAM_CSn_pin => SIG_0_Generic_SDRAM_SDRAM_CSn_pin, fpga_0_Generic_SDRAM_SDRAM_CASn_pin => SIG_0_Generic_SDRAM_SDRAM_CASn_pin, fpga_0_Generic_SDRAM_SDRAM_RASn_pin => SIG_0_Generic_SDRAM_SDRAM_RASn_pin, fpga_0_Generic_SDRAM_SDRAM_Clk_pin => SIG_0_Generic_SDRAM_SDRAM_Clk_pin, fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin => SIG_0_Generic_SDRAM_SDRAM_BankAddr_pin, sys_clk_pin => sys_clk_pin, sys_rst_pin => not auto_rst --- auto reset ); --- TEST POINT OUTPUT -- TP_A0 <= SIG_0_Generic_SDRAM_SDRAM_Addr_pin(0); -- IOB40 CN1.57 TP_RAS <= SIG_0_Generic_SDRAM_SDRAM_RASn_pin; -- IOB41 CN1.58 TP_CAS <= SIG_0_Generic_SDRAM_SDRAM_CASn_pin; -- IOB42 CN1.59 TP_WE <= SIG_0_Generic_SDRAM_SDRAM_WEn_pin; -- IOB43 CN1.60 TP_CS <= SIG_0_Generic_SDRAM_SDRAM_CSn_pin; -- IOB44 CN1.61 TP_1 <= SIG_0_Generic_SDRAM_SDRAM_Clk_pin; -- IOB45 CN1.62 TP_2 <= '0'; -- IOB46 CN1.63 TP_3 <= SIG_0_Generic_SDRAM_SDRAM_Addr_pin(1); -- IOB47 CN1.64 --- NODE CONNECTIION -- monit_data <= SIG_0_Generic_SDRAM_SDRAM_DQ_pin ; internal_obf_clk <= SIG_0_Generic_SDRAM_SDRAM_Clk_pin; dummy_node <= sdram_clk_fb_pin ; -- not use --- PIN CONNECTION -- fpga_0_Generic_SDRAM_SDRAM_DQ_pin <= SIG_0_Generic_SDRAM_SDRAM_DQ_pin; fpga_0_Generic_SDRAM_SDRAM_Addr_pin <= SIG_0_Generic_SDRAM_SDRAM_Addr_pin; fpga_0_Generic_SDRAM_SDRAM_DQM_pin <= SIG_0_Generic_SDRAM_SDRAM_DQM_pin; fpga_0_Generic_SDRAM_SDRAM_WEn_pin <= SIG_0_Generic_SDRAM_SDRAM_WEn_pin; fpga_0_Generic_SDRAM_SDRAM_CKE_pin <= SIG_0_Generic_SDRAM_SDRAM_CKE_pin; fpga_0_Generic_SDRAM_SDRAM_CSn_pin <= SIG_0_Generic_SDRAM_SDRAM_CSn_pin; fpga_0_Generic_SDRAM_SDRAM_CASn_pin <= SIG_0_Generic_SDRAM_SDRAM_CASn_pin; fpga_0_Generic_SDRAM_SDRAM_RASn_pin <= SIG_0_Generic_SDRAM_SDRAM_RASn_pin; fpga_0_Generic_SDRAM_SDRAM_Clk_pin <= SIG_0_Generic_SDRAM_SDRAM_Clk_pin; fpga_0_Generic_SDRAM_SDRAM_BankAddr_pin <= SIG_0_Generic_SDRAM_SDRAM_BankAddr_pin; end RTL;