--*** *-- --** HumanData Ltd. **-- --* by K.N ***-- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PLSGEN is --- --- when using system clock as 18.432MHz --- --- 115200 bps => TX_WIDTH= 8 RX_WIDTH= 4 N= 160 --- 57600 bps => TX_WIDTH= 9 RX_WIDTH= 5 N= 320 --- 38400 bps => TX_WIDTH= 9 RX_WIDTH= 5 N= 480 --- 19200 bps => TX_WIDTH=10 RX_WIDTH= 6 N= 960 --- 14400 bps => TX_WIDTH=11 RX_WIDTH= 7 N= 1280 --- 9600 bps => TX_WIDTH=11 RX_WIDTH= 7 N= 1920 --- 4800 bps => TX_WIDTH=12 RX_WIDTH= 8 N= 3840 --- 2400 bps => TX_WIDTH=13 RX_WIDTH= 9 N= 7680 --- 1200 bps => TX_WIDTH=14 RX_WIDTH=10 N=15360 -- To change a baudrate ---------------- generic ( TX_WIDTH : integer := 8; RX_WIDTH : integer := 4; N : integer := 160 ); ---------------------------------------- port ( CLK : in std_logic; TX_RDY : in std_logic; RX_RDY : in std_logic; TX_ENB : out std_logic; RX_ENB : out std_logic ); end PLSGEN; architecture RTL of PLSGEN is signal TX_CNT : std_logic_vector( TX_WIDTH - 1 downto 0 ); signal RX_CNT : std_logic_vector( RX_WIDTH - 1 downto 0 ); begin process( CLK, TX_RDY ) begin if( TX_RDY = '0') then TX_CNT <= conv_std_logic_vector( N - 3 , TX_WIDTH ); elsif( CLK'event and CLK = '1') then if( TX_CNT = N - 1 ) then TX_CNT <= (others=>'0'); TX_ENB <= '1'; else TX_CNT <= TX_CNT + '1'; TX_ENB <= '0'; end if; end if; end process; process( CLK, RX_RDY ) begin if( RX_RDY = '0') then RX_CNT <= conv_std_logic_vector( (N/16)-3 , RX_WIDTH ); elsif( CLK'event and CLK = '1') then if( RX_CNT = (N/16)-1 ) then RX_CNT <= (others=>'0'); RX_ENB <= '1'; else RX_CNT <= RX_CNT + '1'; RX_ENB <= '0'; end if; else NULL; end if; end process; end RTL;