--***                  *--
--**  RS232C_MEM_TOP  **--
--*                  ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232C_MEM_TOP is
	Port ( CLK  : in  std_logic; -- SYSTEM CLOCK
			 SW2  : in  std_logic; -- RESET
			 RXD  : in  std_logic; 
			 TXD  : out std_logic;
			 LED  : out std_logic_vector( 6 downto 0 );
			 SA   : out std_logic_vector( 5 downto 0 ) );
end RS232C_MEM_TOP;

architecture RTL of RS232C_MEM_TOP is

component RS232C_CLKGEN
	Port ( CLK   : in  std_logic;
			 RST   : in  std_logic;
			 TX_EN : out std_logic;
			 RX_EN : out std_logic );
end component;

component RS232C_RX
    Port ( CLK  : in  std_logic;
           RST  : in  std_logic;
	 		  CE   : in  std_logic;
           DIN  : in  std_logic;
			  RD   : out std_logic;
           DOUT : out std_logic_vector( 7 downto 0 ) );
end component;

component RS232C_TX
    Port ( CLK  : in  std_logic;
           RST  : in  std_logic;
	 		  CE   : in  std_logic;
			  WR   : in  std_logic;
           DIN  : in  std_logic_vector(7 downto 0);
           DOUT : out std_logic );
end component;

component SEG_CTL
	port( CLK, CE, RST           : in  std_logic;
			DATA_A, DATA_B, DATA_C, 
			DATA_D, DATA_E, DATA_F : in  std_logic_vector( 3 downto 0 );
			DATA_OUT               : out std_logic_vector( 6 downto 0 );
			SA                     : out std_logic_vector( 5 downto 0 ) );
end component;

component MEMORY_CONTROL is
	Port ( CLK        : in  std_logic;
			 RST        : in  std_logic;
			 RDSTB      : in  std_logic;
          IN_ASCII   : in  std_logic_vector( 7 downto 0 );
			 OUT_ADRS   : out std_logic_vector( 7 downto 0 );
			 OUT_HIBYTE : out std_logic_vector( 7 downto 0 );
			 OUT_LOBYTE : out std_logic_vector( 7 downto 0 ) );
end component;

	signal TX_EN  : std_logic;
	signal RX_EN  : std_logic;
	signal RST    : std_logic;
	signal RDEN   : std_logic;
	signal BYTE   : std_logic_vector( 7 downto 0 ); 

	signal ADRS   : std_logic_vector( 7 downto 0 );
	signal HIBYTE : std_logic_vector( 7 downto 0 );
	signal LOBYTE : std_logic_vector( 7 downto 0 );

begin

	RST <= not SW2;

	U1 : RS232C_CLKGEN port map ( CLK, RST, TX_EN, RX_EN );
	U2 : RS232C_RX     port map ( CLK, RST, RX_EN, RXD, RDEN, BYTE );
	U3 : RS232C_TX     port map ( CLK, RST, TX_EN, RDEN, BYTE, TXD );

	U4 : SEG_CTL port map ( CLK, TX_EN, RST,
		                     LOBYTE(3 downto 0), LOBYTE(7 downto 4),
		                     HIBYTE(3 downto 0), HIBYTE(7 downto 4),
		                     ADRS  (3 downto 0), ADRS  (7 downto 4),
									LED, SA );

	U5 : MEMORY_CONTROL port map( CLK, RST, RDEN, BYTE, ADRS, HIBYTE, LOBYTE );



end RTL;