--***                 *--
--**  RS232C_CLKGEN  **--
--*                 ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232C_CLKGEN is
	Port ( CLK   : in  std_logic;
			 RST   : in  std_logic;
			 TX_EN : out std_logic;
			 RX_EN : out std_logic );
end RS232C_CLKGEN;

architecture RTL of RS232C_CLKGEN is
	signal TX_CNT : std_logic_vector( 7 downto 0 ); 
	signal RX_CNT : std_logic_vector( 3 downto 0 ); 

begin
	
	process( CLK ) begin
		if( CLK'event and CLK = '1') then
			if( RST = '1') then ---
				TX_CNT <= (others=>'0');
			elsif( TX_CNT = "10011111") then
				TX_CNT <= (others=>'0');
				TX_EN  <= '1';
			else
				TX_CNT <= TX_CNT + '1';
				TX_EN  <= '0';
			end if; ---
		end if; 
	end process;

	process( CLK ) begin
		if( CLK'event and CLK = '1') then
			if( RST = '1') then ---
				RX_CNT <= (others=>'0');
			elsif( RX_CNT = "1001") then
				RX_CNT <= (others=>'0');
				RX_EN  <= '1';
			else
				RX_CNT <= RX_CNT + '1';
				RX_EN  <= '0';
			end if; ---
		end if;
	end process;
end RTL;

--***             *--
--**  RS232C_TX  **--
--*             ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232C_TX is
    Port ( CLK  : in  std_logic;
           RST  : in  std_logic;
	 		  CE   : in  std_logic;
			  WR   : in  std_logic;
           DIN  : in  std_logic_vector(7 downto 0);
           DOUT : out std_logic );
end RS232C_TX;

architecture RTL of RS232C_TX is
	signal IN_DIN : std_logic_vector( 7 downto 0 ); 
	signal LOAD   : std_logic;
	signal CBIT   : integer range 0 to 9;

begin
	process( CLK ) begin
		if( CLK'event and CLK='1') then
			if( RST = '1') then
				LOAD <= '0';
				CBIT <=  0 ;
				DOUT <= '1';
			elsif( WR = '1' ) then
				LOAD   <= '1';
				IN_DIN <= DIN;
			elsif( CE = '1' and LOAD = '1' ) then
				case CBIT is
					when 0 => 
						DOUT <= '0';
						CBIT <= CBIT + 1;
					when 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => 
						DOUT   <= IN_DIN(0);
						IN_DIN <= '1' & IN_DIN(7 downto 1);
						CBIT   <= CBIT + 1;
					when others => 
						DOUT <= '1';
						LOAD <= '0';
						CBIT <=  0;
				end case;
			end if;
		end if;
	end process;

end RTL;

--***             *--
--**  RS232C_RX  **--
--*             ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232C_RX is
    Port ( CLK  : in  std_logic;
           RST  : in  std_logic;
	 		  CE   : in  std_logic;
           DIN  : in  std_logic;
			  RD   : out std_logic;
           DOUT : out std_logic_vector( 7 downto 0 ) );
end RS232C_RX;

architecture RTL of RS232C_RX is
	signal PARALLEL : std_logic_vector( 7 downto 0 );
	signal SERIAL   : std_logic;
	signal START    : std_logic;
	signal RDI      : std_logic;
	signal CBIT     : integer range 0 to 142;

begin
	process( CLK ) begin
		if( CLK'event and CLK='1') then
			if( RST = '1') then
				START <= '0';
				CBIT  <=  0 ;
				PARALLEL <= (others=>'0');
				DOUT     <= (others=>'0');
			elsif( CE = '1') then
				RDI <= '0';

				if( START = '0') then
					if( DIN = '0') then
						START  <= '1';
					end if;
				else
					SERIAL <= DIN;

					case CBIT is
						when 6 => --start
							if( SERIAL = '1') then
								START <= '0';
							else
								CBIT <= CBIT + 1;
							end if;
						when 22 | 38 | 54 | 70 | 86 | 102 | 118 | 134 => --data
							CBIT     <= CBIT + 1;
							PARALLEL <= SERIAL & PARALLEL(7 downto 1);						
						when 142  => --stop
							CBIT  <= 0;
							DOUT  <= PARALLEL;
							START <= '0';
							RDI   <= '1';
						when others =>
							CBIT <= CBIT + 1;
					end case;
				end if;
			end if;		
		end if;
	end process;

	RD <= RDI and CE;

end RTL;