--***                  *--
--**  MEMORY_CONTROL  **--
--*                  ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MEMORY_CONTROL is
	Port ( CLK        : in  std_logic;
			 RST        : in  std_logic;
			 RDSTB      : in  std_logic;
          IN_ASCII   : in  std_logic_vector( 7 downto 0 );
			 OUT_ADRS   : out std_logic_vector( 7 downto 0 );
			 OUT_HIBYTE : out std_logic_vector( 7 downto 0 );
			 OUT_LOBYTE : out std_logic_vector( 7 downto 0 ) );
end MEMORY_CONTROL;

architecture RTL of MEMORY_CONTROL is

component RAM is 
	port ( CLK  : in  std_logic; 
			 WE   : in  std_logic; 
 		    ADRS : in  std_logic_vector( 7 downto 0); 
 		    DI   : in  std_logic_vector(15 downto 0); 
 		    DO   : out std_logic_vector(15 downto 0)); 
end component; 

component CONV_ASCII_TO_BIN is 
    Port ( ASCII : in  std_logic_vector( 7 downto 0 );
	 	     BYTE  : out std_logic_vector( 3 downto 0 ));
end component; 

	signal HALF_ADRS  : std_logic_vector( 3 downto 0 );
	signal ADRS       : std_logic_vector(  7 downto 0 ); 
	signal MEMORY_IN  : std_logic_vector( 15 downto 0 ); 
	signal MEMORY_OUT : std_logic_vector( 15 downto 0 );
	signal MEMORY_WE  : std_logic;

	signal BIT4  : std_logic_vector( 3 downto 0 );
	signal BIT8  : std_logic_vector( 7 downto 0 );
	signal BIT12 : std_logic_vector(11 downto 0 );

	signal HEX   : std_logic_vector( 3 downto 0 );

	signal TERM_CNT  : integer range 0 to 7;

	constant ASC_W : std_logic_vector( 7 downto 0 ) := "01010111";
	constant ASC_R : std_logic_vector( 7 downto 0 ) := "01010010";
	constant ASC_CR: std_logic_vector( 7 downto 0 ) := "00001101";
begin
	
	U0 : RAM port map( CLK, MEMORY_WE, ADRS, MEMORY_IN, MEMORY_OUT );
	U1 : CONV_ASCII_TO_BIN port map( IN_ASCII, HEX );

	-- STATE MACHINE
	-- MEMORY READ / WRITE 
	process( CLK ) begin
		if( CLK'event and CLK = '1') then
			if( RST = '1') then
				TERM_CNT <= 0;
			elsif( RDSTB = '1') then

				MEMORY_WE  <= '0';

				case TERM_CNT is
					when 0 => if( IN_ASCII = ASC_R or IN_ASCII = ASC_W ) then
									 TERM_CNT <= 1;
								 else
									 TERM_CNT <= 0;
								 end if;
					when 1 => 
						HALF_ADRS <= HEX;
						TERM_CNT  <= TERM_CNT + 1;
					when 2 =>
						ADRS      <= HALF_ADRS & HEX;
						TERM_CNT  <= TERM_CNT + 1;
					when 3 => if( IN_ASCII = ASC_CR ) then -- READ
									 OUT_ADRS   <= ADRS; -- ADDRESS
									 OUT_HIBYTE <= MEMORY_OUT(15 downto 8); -- LOWORD
									 OUT_LOBYTE <= MEMORY_OUT( 7 downto 0); -- HIWORD
									 TERM_CNT   <= 0;
								 else
									 BIT4     <= HEX;
									 TERM_CNT <= TERM_CNT + 1;
								 end if;
					when 4 =>
						BIT8     <= BIT4 & HEX;						
						TERM_CNT <= TERM_CNT + 1;
					when 5 =>
						BIT12    <= BIT8 & HEX;		  
						TERM_CNT <= TERM_CNT + 1;
				   when 6 =>
						MEMORY_IN <= BIT12 & HEX;
						TERM_CNT  <= TERM_CNT + 1;
					when 7 => if( IN_ASCII = ASC_CR ) then
									  OUT_ADRS   <= ADRS; -- ADDRESS
									  OUT_HIBYTE <= MEMORY_OUT(15 downto 8); -- LOWORD
									  OUT_LOBYTE <= MEMORY_OUT( 7 downto 0); -- HIWORD
									  MEMORY_WE  <= '1';
									  TERM_CNT <=  0;
								 else
									  OUT_ADRS   <= "XXXXXXXX"; -- ADDRESS
									  OUT_HIBYTE <= "XXXXXXXX"; -- LOWORD
									  OUT_LOBYTE <= "XXXXXXXX"; -- HIWORD
									  MEMORY_WE  <= '0';
									  TERM_CNT   <=  0;
								 end if;
					when others => TERM_CNT  <= 0;
				end case;
			end if;
		end if;
	end process;

end RTL;

--***                     *--
--**  CONV_ASCII_TO_BIN  **--
--*                     ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONV_ASCII_TO_BIN is
    Port ( ASCII : in  std_logic_vector( 7 downto 0 );
	 	     BYTE  : out std_logic_vector( 3 downto 0 ) );
end CONV_ASCII_TO_BIN;

architecture RTL of CONV_ASCII_TO_BIN is

	constant ASC_ZERO : std_logic_vector( 7 downto 0 ) := "00110000"; -- 0x30
	constant ASC_NINE : std_logic_vector( 7 downto 0 ) := "00111001"; -- 0x39
   constant ASC_UA   : std_logic_vector( 7 downto 0 ) := "01000001"; -- 0x41
	constant ASC_UF   : std_logic_vector( 7 downto 0 ) := "01000110"; -- 0x46
	constant ASC_LA   : std_logic_vector( 7 downto 0 ) := "01100001"; -- 0x61
	constant ASC_LF   : std_logic_vector( 7 downto 0 ) := "01100110"; -- 0x66
 
begin
	
	process( ASCII ) begin
		if( ASC_ZERO <= ASCII and ASCII <= ASC_NINE ) then
			BYTE <= ASCII( 3 downto 0 );
		elsif( ASC_UA <= ASCII and ASCII <= ASC_UF ) then
			BYTE <= ASCII( 3 downto 0 ) + "1001";
		elsif( ASC_LA <= ASCII and ASCII <= ASC_LF ) then
			BYTE <= ASCII( 3 downto 0 ) + "1001";
		else
			BYTE <= "XXXX";
		end if;
	end process;

end RTL;

--***       *--
--**  RAM  **--
--*       ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity RAM is 
	port ( CLK  : in std_logic; 
			 WE   : in  std_logic; 
 		    ADRS : in  std_logic_vector( 7 downto 0); 
 		    DI   : in  std_logic_vector(15 downto 0); 
 		    DO   : out std_logic_vector(15 downto 0)); 
	end RAM; 
 
architecture RTL of RAM is
  
 	type WORD is array (255 downto 0) of std_logic_vector (15 downto 0);
	signal MEM       : WORD; 
	signal READ_ADRS : std_logic_vector(7 downto 0); 
 
begin 
	process (CLK) begin
 	if (CLK'event and CLK = '1') then  
 		if (WE = '1') then 
 			MEM( conv_integer(ADRS) ) <= DI; 
 		end if;
			READ_ADRS <= ADRS; 
 		end if; 
 	end process; 
 
	DO <= MEM( conv_integer( READ_ADRS ) );
 
end RTL;