--***           *--
--**  SEG_CTL  **--
--*           ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SEG_CTL is
	port( CLK, CE, RST           : in  std_logic;
			DATA_A, DATA_B, DATA_C, 
			DATA_D, DATA_E, DATA_F : in  std_logic_vector( 3 downto 0 );
			DATA_OUT               : out std_logic_vector( 6 downto 0 );
			SA                     : out std_logic_vector( 5 downto 0 ) );
end SEG_CTL;

architecture RTL of SEG_CTL is

component DECODER
	port ( D_IN  : in  std_logic_vector( 3 downto 0 );
	       D_OUT : out std_logic_vector( 6 downto 0 ) );
end component;

component SEG_MUX
	port( DATA_A, DATA_B, DATA_C,
         DATA_D, DATA_E, DATA_F : in  std_logic_vector( 6 downto 0 );
			SEL                    : in  std_logic_vector( 2 downto 0 );
			DATA_OUT               : out std_logic_vector( 6 downto 0 );
			SA                     : out std_logic_vector( 5 downto 0 ) );
end component;

component SEG_CNT
	port ( CLK   : in  std_logic; 
	       CE    : in  std_logic;
			 RST   : in  std_logic;
			 COUNT : out std_logic_vector( 2 downto 0 ) );
end component;

signal DEC_A, DEC_B, DEC_C, DEC_D, DEC_E, DEC_F : std_logic_vector( 6 downto 0 );
signal SEL : std_logic_vector( 2 downto 0 );

begin
	U0 : DECODER port map ( DATA_A, DEC_A );
	U1 : DECODER port map ( DATA_B, DEC_B );
	U2 : DECODER port map ( DATA_C, DEC_C );
	U3 : DECODER port map ( DATA_D, DEC_D );
	U4 : DECODER port map ( DATA_E, DEC_E );
	U5 : DECODER port map ( DATA_F, DEC_F );

	U6 : SEG_CNT port map ( CLK, CE, RST, SEL );
	U7 : SEG_MUX port map ( DEC_A, DEC_B, DEC_C, DEC_D, DEC_E, DEC_F, SEL, DATA_OUT, SA );
end RTL;

--***           *--
--**  SEG_CNT  **--
--*           ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SEG_CNT is
	port ( CLK, CE, RST : in  std_logic;
			 COUNT        : out std_logic_vector( 2 downto 0 ) );
end SEG_CNT;

architecture RTL of SEG_CNT is
signal COUNT_IN : std_logic_vector( 2 downto 0 );

begin

	COUNT <= COUNT_IN;
 
	process( CLK ) begin
		if( CLK' event and CLK = '1' ) then
			if( RST = '1') then ---
				COUNT_IN <= "000"; 				
			elsif( CE = '1') then 
				if( COUNT_IN = "101" ) then --**
					COUNT_IN <= "000";
				else
					COUNT_IN <= COUNT_IN + '1';
				end if; --**
			end if; ---
		end if;
	end process;
end RTL;

--***           *--
--**  SEG_MUX  **--
--*           ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SEG_MUX is
	port( DATA_A, DATA_B, DATA_C,
         DATA_D, DATA_E, DATA_F : in  std_logic_vector( 6 downto 0 );
			SEL                    : in  std_logic_vector( 2 downto 0 );
			DATA_OUT               : out std_logic_vector( 6 downto 0 );
			SA                     : out std_logic_vector( 5 downto 0 ) );

end SEG_MUX;

architecture RTL of SEG_MUX is
begin
	DATA_OUT <= DATA_A when SEL = "000" else
					DATA_B when SEL = "001" else
					DATA_C when SEL = "010" else
					DATA_D when SEL = "011" else
					DATA_E when SEL = "100" else DATA_F;

	SA       <= "0ZZZZZ" when SEL = "000" else 
	            "Z0ZZZZ" when SEL = "001" else
					"ZZ0ZZZ" when SEL = "010" else
					"ZZZ0ZZ" when SEL = "011" else
					"ZZZZ0Z" when SEL = "100" else 
					"ZZZZZ0" when SEL = "101" else "ZZZZZZ";
end RTL;

--***           *--
--**  DECODER  **--
--*           ***--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER is
	port ( D_IN  : in  std_logic_vector( 3 downto 0 );
	       D_OUT : out std_logic_vector( 6 downto 0 ) );
end DECODER;

architecture RTL of DECODER is 
begin
	process( D_IN ) begin
			case D_IN is			
		 	when "0000" => D_OUT <= "1000000"; -- 0
			when "0001" => D_OUT <= "1111001"; -- 1
			when "0010" => D_OUT <= "0100100"; -- 2
			when "0011" => D_OUT <= "0110000"; -- 3
	
			when "0100" => D_OUT <= "0011001"; -- 4
			when "0101" => D_OUT <= "0010010"; -- 5
			when "0110" => D_OUT <= "0000010"; -- 6
			when "0111" => D_OUT <= "1111000"; -- 7
	
			when "1000" => D_OUT <= "0000000"; -- 8
			when "1001" => D_OUT <= "0010000"; -- 9
			when "1010" => D_OUT <= "0001000"; -- a
			when "1011" => D_OUT <= "0000011"; -- b
	
			when "1100" => D_OUT <= "1000110"; -- c
			when "1101" => D_OUT <= "0100001"; -- d
			when "1110" => D_OUT <= "0000110"; -- e
			when "1111" => D_OUT <= "0001110"; -- f
			when others => NULL;
			end case;
	end process;
end RTL;