-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY DET1 IS 
	port
	(
		CLK :  IN  STD_LOGIC;
		INA :  IN  STD_LOGIC;
		INB :  IN  STD_LOGIC;
		DET :  OUT  STD_LOGIC
	);
END DET1;

ARCHITECTURE bdf_type OF DET1 IS 

component bibun
	PORT(INP : IN STD_LOGIC;
		 CLK : IN STD_LOGIC;
		 OUTP : OUT STD_LOGIC
	);
end component;

signal	BBINA :  STD_LOGIC;
signal	BBINB :  STD_LOGIC;
signal	BINA :  STD_LOGIC;
signal	BINB :  STD_LOGIC;
signal	BNA :  STD_LOGIC;
signal	BNB :  STD_LOGIC;
signal	NA :  STD_LOGIC;
signal	NB :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;


BEGIN 



SYNTHESIZED_WIRE_1 <= NA XOR NB;

process(CLK)
begin
if (rising_edge(CLK)) then
	DET <= SYNTHESIZED_WIRE_0;
end if;
end process;

NA <= BINA AND INB;

NB <= INA AND BINB;

b2v_inst12 : bibun
PORT MAP(INP => SYNTHESIZED_WIRE_1,
		 CLK => CLK,
		 OUTP => SYNTHESIZED_WIRE_8);

BNA <= BBINA AND SYNTHESIZED_WIRE_9;

BNB <= SYNTHESIZED_WIRE_10 AND BBINB;

b2v_inst15 : bibun
PORT MAP(INP => SYNTHESIZED_WIRE_10,
		 CLK => CLK,
		 OUTP => BBINA);

b2v_inst16 : bibun
PORT MAP(INP => SYNTHESIZED_WIRE_9,
		 CLK => CLK,
		 OUTP => BBINB);

b2v_inst17 : bibun
PORT MAP(INP => SYNTHESIZED_WIRE_6,
		 CLK => CLK,
		 OUTP => SYNTHESIZED_WIRE_7);

SYNTHESIZED_WIRE_6 <= BNA XOR BNB;

SYNTHESIZED_WIRE_10 <= NOT(INA);


SYNTHESIZED_WIRE_9 <= NOT(INB);


SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_7 OR SYNTHESIZED_WIRE_8;

b2v_inst8 : bibun
PORT MAP(INP => INA,
		 CLK => CLK,
		 OUTP => BINA);

b2v_inst9 : bibun
PORT MAP(INP => INB,
		 CLK => CLK,
		 OUTP => BINB);

END;